NXP Semiconductors MWCT101 S Series, Reference Manual

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Note
The FTM counter is clocked by the phase A and B input signals
when quadrature decoder mode is enabled. Therefore it is
expected that the quadrature decoder mode be used only with
the FTM channels in input capture or output compare modes.
Note
An edge at phase A must not occur together an edge at phase B
and vice-versa.
The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects
the polarity of the phase B input.
The QUADMODE selects the encoding mode used in the quadrature decoder mode. If
QUADMODE = 1, then the count and direction encoding mode is enabled; see the
following figure. In this mode, the phase B input value indicates the counting direction,
and the phase A input defines the counting rate. The FTM counter is updated when there
is a rising edge at phase A input signal.
phase B (counting direction)
phase A (counting rate)
FTM counter
increment/decrement
FTM counter
MOD
CNTIN
0x0000
Time
+1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1
Figure 41-103. Quadrature Decoder – Count and Direction Encoding mode
If QUADMODE = 0, then the phase A and phase B Encoding mode is enabled; see the
following figure. In this mode, the relationship between phase A and B signals indicates
the counting direction, and phase A and B signals define the counting rate. The FTM
counter is updated when there is an edge either at the phase A or phase B signals.
If PHAPOL = 0 and PHBPOL = 0, then the FTM counter increment happens when:
• there is a rising edge at phase A signal and phase B signal is at logic zero;
• there is a rising edge at phase B signal and phase A signal is at logic one;
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1267