NXP Semiconductors MWCT101 S Series, Reference Manual

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Program flash
Flash memory configuration field
FlexNVM base address
Program flash memory base address
Flash memory base address
Registers
FlexNVM
FlexRAM
FlexRAM base address
memory
Figure 3-1. Flash memory map
3.4 Peripheral bridge (AIPS-Lite) memory map
The peripheral memory map is accessible via a crossbar slave port.
There are three regions associated with peripheral space, as shown in the following table.
Table 3-1. Regions associated with peripheral space
Address space Region description
0x4000_0000–0x4001_FFFF A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on-
platform peripheral devices. AIPS-Lite generates unique module enables for all 32
spaces.
0x4002_0000–0x4007_FFFF A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off-
platform modules. AIPS-Lite generates unique module enables for all 96 spaces.
0x400F_F000 A 4 KB region for accessing the GPIO module. This block is connected to the
AMBA bus via the port splitter and provides direct master access without incurring
wait states associated with accesses via the AIPS-Lite modules. The GPIO is
implemented only in the upper space of this region (4 KB beginning at
0x400F_F000).
Modules that are disabled via their clock gate control bits in the PCC/SIM registers
disable the associated AIPS-Lite slots. Access to any address within an unimplemented or
disabled peripheral bridge slot results in a transfer error termination.
NOTE
While trying to access memory map region of unavailable
feature (See SIM_SDID[FEATURES]) with corresponding
Peripheral bridge (AIPS-Lite) memory map
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
66 NXP Semiconductors