NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1482 / 1761

Field Function
A character that is in the process of being received does not cause a change in RDRF until the entire
character is received. Even if RDRF is set, the character will continue to be received until an overrun
condition occurs once the entire character is received.
0b - Receive data buffer empty.
1b - Receive data buffer full.
20
IDLE
Idle Line Flag
IDLE is set when the LPUART receive line becomes idle for a full character time after a period of activity.
When CTRL[ILT] is cleared, the receiver starts counting idle bit times after the start bit. If the receive
character is all 1s, these bit times and the stop bits time count toward the full character time of logic high,
10 to 13 bit times, needed for the receiver to detect an idle line. When CTRL[ILT] is set, the receiver
doesn't start counting idle bit times until after the stop bits. The stop bits and any logic high bit times at
the end of the previous character do not count toward the full character time of logic high needed for the
receiver to detect an idle line.
To clear IDLE, write logic 1 to the IDLE flag. After IDLE has been cleared, it cannot be set again until after
a new character has been stored in the receive buffer or a LIN break character has set the LBKDIF flag .
IDLE is set only once even if the receive line remains idle for an extended period.
0b - No idle line detected.
1b - Idle line was detected.
19
OR
Receiver Overrun Flag
OR is set when software fails to prevent the receive data register from overflowing with data. The OR bit
is set immediately after the stop bit has been completely received for the dataword that overflows the
buffer and all the other error flags (FE, NF, and PF) are prevented from setting. The data in the shift
register is lost, but the data already in the LPUART data registers is not affected. If LBKDE is enabled
and a LIN Break is detected, the OR field asserts if LBKDIF is not cleared before the next data character
is received.
While the OR flag is set, no additional data is stored in the data buffer even if sufficient room exists. To
clear OR, write logic 1 to the OR flag.
0b - No overrun.
1b - Receive overrun (new LPUART data lost).
18
NF
Noise Flag
The advanced sampling technique used in the receiver takes three samples in each of the received bits.
If any of these samples disagrees with the rest of the samples within any bit time in the frame then noise
is detected for that character. NF is set whenever the next character to be read from the DATA register
was received with noise detected within the character. To clear NF, write logic 1 to the NF field.
0b - No noise detected.
1b - Noise detected in the received character in the DATA register.
17
FE
Framing Error Flag
FE is set whenever the next character to be read from the DATA register was received with logic 0
detected where a stop bit was expected. To clear FE, write logic 1 to the FE field.
0b - No framing error detected. This does not guarantee the framing is correct.
1b - Framing error.
16
PF
Parity Error Flag
PF is set whenever the next character to be read from the DATA register was received when parity is
enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity
value. To clear PF, write a logic 1 to the PF field.
0b - No parity error.
1b - Parity error.
15
MA1F
Match 1 Flag
Table continues on the next page...
Register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1482 NXP Semiconductors