NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1459 / 1761

The following timing restrictions must be enforced to avoid unexpected START or STOP
conditions on the I2C bus, or to avoid unexpected START or STOP conditions detected
by the LPI2C master. The timing restrictions can be summarized as SDA cannot change
when SCL is high outside of a transmitted (repeated) START or STOP condition.
Table 46-9. LPI2C Timing Parameter Restrictions
Timing Parameter Minimum Maximum Comment
CLKLO 0x03 - Also: CLKLO x (2 ^ PRESCALE) >
SCL_LATENCY
CLKHI 0x01 - Configure CLKHI to meet the duty cycle
requirements in the I2C specification
SETHOLD 0x02 -
DATAVD 0x01 CLKLO - SDA_LATENCY
- 1
Configure DATAVD to meet the data
hold requirement in the I2C specification
FILTSCL 0x00 [CLKLO x (2 ^
PRESCALE)] - 3
FILTSCL and FILTSDA are the only
parameters not multiplied by (2 ^
PRESCALE)
FILTSDA FILTSCL [CLKLO x (2 ^
PRESCALE)] - 3
Configuring FILTSDA greater than
FILTSCL can delay the SDA input to
compensate for board level skew
BUSIDLE (CLKLO+2) x
2
- Must also be greater than (CLKHI+1)
The timing parameters must be configured to meet the requirements of the I2C
specification; this will depend on the mode being supported and the LPI2C functional
clock frequency. When switching between two modes using the different clock
configuration registers (for example, Fast and HS-mode), the PRESCALE factor must
remain constant between the modes. Some example timing configurations are provided
below.
Table 46-10. LPI2C Example Timing Configurations
I2C Mode Clock
Frequency
Baud
Rate
PRESCALE FILTSCL /
FILTSDA
SETHOLD CLKLO CLKHI DATAVD
Fast 8 MHz 400 kbps 0x0 0x0/0x0 0x04 0x0B 0x05 0x02
Fast+ 8 MHz 1 Mbps 0x0 0x0/0x0 0x02 0x03 0x01 0x01
Fast 48 MHz 400 kbps 0x0 0x1/0x1 0x1D 0x3E 0x35 0x0F
Fast 48 MHz 400 kbps 0x2 0x1/0x1 0x07 0x11 0x0B 0x03
Fast+ 48 MHz 1 Mbps 0x2 0x1/0x1 0x03 0x06 0x04 0x04
HS-mode 48 MHz 3.2 Mbps 0x0 0x0/0x0 0x07 0x08 0x03 0x01
Fast 60 MHz 400 kbps 0x1 0x2/0x2 0x11 0x28 0x1F 0x08
Fast+ 60 MHz 1 Mbps 0x1 0x2/0x2 0x07 0x0F 0x0B 0x01
HS-mode 60 MHz 3.33 Mbps 0x1 0x0/0x0 0x04 0x04 0x02 0x01
Chapter 46 Low Power Inter-Integrated Circuit (LPI2C)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1459