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33.4.2.4 Buffer0 Configuration Register (QuadSPI_BUF0CR)
This register provides the configuration for any access to buffer0. An access is routed to
buffer0 when the master port number of the incoming AHB request matches the
MSTRID field of BUF0CR. Any buffer "miss" leads to a serial flash transaction being
triggered as per the sequence pointed to the SEQID field. Buffer0 may also be configured
as a high priority buffer by setting the HP_EN field of this register.
Write:
• QSPI_SR[AHB_ACC] = 0
Address: 4007_6000h base + 10h offset = 4007_6010h
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
* Notes:
MSTRID field: See the module configuration for reset value.
•
QuadSPI_BUF0CR field descriptions
Field
Description
31
HP_EN
High Priority Enable. When set, the master associated with this buffer is assigned a priority higher than the
rest of the masters. An access by a high priority master will suspend any ongoing prefetch by another AHB
master and will be serviced on high priority. Refer to
30–16
Reserved
This field is reserved.
15–8
ADATSZ
AHB data transfer size
Defines the data transfer size in 8 bytes of an AHB triggered access to serial flash. For example, a value
of 0x2 will set transfer size to 16 bytes. When ADATSZ = 0, the data size mentioned the sequence pointed
to by the SEQID field overrides this value. Software should ensure that this transfer size is not greater
than the size of this buffer.
7–4
Reserved
This field is reserved.
MSTRID
Master ID. The ID of the AHB master associated with BUFFER0. Any AHB access with this master port
number is routed to this buffer. It must be ensured that the master IDs associated with all buffers must be
different.
Memory Map and Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
846
NXP Semiconductors
Summary of Contents for MWCT101 S Series
Page 2: ...MWCT101xS Series Reference Manual Rev 3 07 2019 2 NXP Semiconductors...
Page 42: ...MWCT101xS Series Reference Manual Rev 3 07 2019 42 NXP Semiconductors...
Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
Page 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...
Page 960: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 960 NXP Semiconductors...
Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
Page 1348: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1348 NXP Semiconductors...
Page 1366: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1366 NXP Semiconductors...
Page 1514: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1514 NXP Semiconductors...
Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
Page 1760: ...MWCT101xS Series Reference Manual Rev 3 07 2019 1760 NXP Semiconductors...