NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 347 / 1761

16.4.5.31.1 Offset
For n = 0 to 15:
Register Offset
TCDn_CSR 101Ch + (n × 20h)
16.4.5.31.2 Diagram
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BWC
MAJORLINKCH
DONE
ACTIVE
MAJORELINK
ES G
DREQ
INTHALF
INTMAJOR
START
W
0
Reset
u u u u u u u u u u u u u u u u
16.4.5.31.3 Fields
Field Function
15-14
BWC
Bandwidth Control
Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00b - No eDMA engine stalls.
01b - Reserved
10b - eDMA engine stalls for 4 cycles after each R/W.
11b - eDMA engine stalls for 8 cycles after each R/W.
13-12
—
Reserved
11-8
MAJORLINKCH
Major Loop Link Channel Number
If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel's TCDn_CSR[START] bit.
7
DONE
Channel Done
Table continues on the next page...
Chapter 16 Enhanced Direct Memory Access (eDMA)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 347