NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 466 / 1761

to the CNT register. Both methods must occur before the WDG timeout; otherwise, the
watchdog resets the MCU.
Note
Before starting the refresh sequence, disable the global
interrupts. Otherwise, an interrupt could effectively invalidate
the refresh sequence, if the interrupt occurs before the refresh
writes finish. After the sequence finishes, restore the global
interrupt control state.
The example codes can be found at the end of this chapter.
Configuring the Watchdog
21.4.3.1 Configuring the Watchdog Once
All watchdog control bits, timeout value, and window value are write-once after
reset . This means that after a write has occurred they cannot be changed unless a
reset occurs. This is guaranteed by the user configuring the window and timeout value
first, followed by the other control bits, and ensuring that CS[UPDATE] is also set to 0.
This provides a robust mechanism to configure the watchdog and ensure that a runaway
condition cannot mistakenly disable or modify the watchdog configuration after
configured.
The new configuration takes effect only after all registers except CNT are written after
reset. Otherwise, the WDOG uses the reset values by default. If window mode is not used
(CS[WIN] is 0), writing to WIN is not required to make the new configuration take
effect.
21.4.3.2 Reconfiguring the Watchdog
In some cases (like when supporting a bootloader function), you may want to reconfigure
or disable the watchdog, without forcing a reset first.
• By setting CS[UPDATE] to 1 on the initial configuration of the watchdog after a
reset, you can reconfigure the watchdog at any time by executing an unlock
sequence.
• Conversely, if CS[UPDATE] remains 0, the only way to reconfigure the watchdog is
by initiating a reset.
The unlock sequence is similar to the refresh sequence but uses different values.
21.4.3
Configuring the Watchdog
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
466 NXP Semiconductors