NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1301 / 1761

Memory Map and Registers
42.4.1 LPIT register descriptions
The memory map comprises of 32-bit aligned registers, which can be accessed via 8-bit,
16-bit, or 32-bit accesses.
• Write access to reserved locations will generate a transfer error.
• Read access to reserved locations will also generate a transfer error, and the read data
bus will show all 0s.
NOTE
• The Memory Map and complete module is in Big Endian
format.
• The LPIT module will not check if programmed values in
the registers are correct; software must ensure that correct
programmed values are being written.
42.4.1.1 LPIT Memory map
LPIT base address: 4003_7000h
Offset Register Width
(In bits)
Access Reset value
0h Version ID Register (VERID) 32 RO 0100_0000h
4h Parameter Register (PARAM) 32 RO 0000_0404h
8h Module Control Register (MCR) 32 RW 0000_0000h
Ch Module Status Register (MSR) 32 W1C 0000_0000h
10h Module Interrupt Enable Register (MIER) 32 RW 0000_0000h
14h Set Timer Enable Register (SETTEN) 32 RW 0000_0000h
18h Clear Timer Enable Register (CLRTEN) 32 WORZ 0000_0000h
20h Timer Value Register (TVAL0) 32 RW 0000_0000h
24h Current Timer Value (CVAL0) 32 RO FFFF_FFFFh
28h Timer Control Register (TCTRL0) 32 RW 0000_0000h
30h Timer Value Register (TVAL1) 32 RW 0000_0000h
34h Current Timer Value (CVAL1) 32 RO FFFF_FFFFh
38h Timer Control Register (TCTRL1) 32 RW 0000_0000h
40h Timer Value Register (TVAL2) 32 RW 0000_0000h
Table continues on the next page...
42.4
Chapter 42 Low Power Interrupt Timer (LPIT)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1301