NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1340 / 1761

43.4.1.3 Low Power Timer Prescale Register (PSR)
43.4.1.3.1 Offset
Register Offset
PSR 4h
43.4.1.3.2 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PRESCAL E
PBY P
PC S
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
43.4.1.3.3 Fields
Field Function
31-7
—
Reserved
6-3
PRESCALE
Prescale Value
Configures the size of the Prescaler in Time Counter mode or width of the glitch filter in Pulse Counter
mode. The width of the glitch filter can vary by 1 cycle due to synchronization of the pulse counter input.
PRESCALE must be altered only when the LPTMR is disabled.
0000b - Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
0001b - Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after
2 rising clock edges.
0010b - Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after
4 rising clock edges.
0011b - Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin
after 8 rising clock edges.
0100b - Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin
after 16 rising clock edges.
0101b - Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin
after 32 rising clock edges.
0110b - Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin
after 64 rising clock edges.
Table continues on the next page...
Memory map and register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1340 NXP Semiconductors