NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1455 / 1761

46.4.1 Clocking and Resets
Table 46-5. Clocks
LPI2C Functional clock The LPI2C functional clock is asynchronous to the bus clock and can remain enabled in low power
modes to support I2C bus transfers by the LPI2C master. The functional clock is also used by the
LPI2C slave to support digital filter and data hold time configurations. The LPI2C master divides the
functional clock by a prescaler and the resulting frequency must be at least 8 times faster than the
I2C bus bandwidth.
External clock The LPI2C slave logic is clocked directly from the external pins SCL and SDA (or SCLS and SDAS
if master and slave are implemented on separate pins). This allows the LPI2C slave to remain
operational, even when the LPI2C functional clock is disabled.
NOTE: The LPI2C slave digital filter must be disabled if the LPI2C functional clock is disabled, and
this can affect compliance with some of the timing parameters of the I2C specification,
such as the data hold time.
Bus clock The bus clock is only used for bus accesses to the control and configuration registers. The bus
clock frequency must be sufficient to support the data bandwidth requirements of the LPI2C master
and slave registers.
Table 46-6. Resets
Chip reset The logic and registers for the LPI2C master and slave are reset to their default state on a chip
reset.
Software reset • The LPI2C master implements a software reset bit in its Control Register. The MCR[RST] will
reset all master logic and registers to their default state, except for the MCR itself.
• The LPI2C slave implements a software reset bit in its Control Register. The SCR[RST] will
reset all slave logic and registers to their default state, except for the SCR itself.
FIFO reset • The LPI2C master implements write-only control bits that reset the transmit FIFO (MCR[RTF])
and receive FIFO (MCR[RRF]). After a FIFO is reset, that FIFO is empty.
• The LPI2C slave implements write-only control bits that reset the transmit data register
(SCR[RTF] and receive data register (SCR[RRF]). After a data register is reset, that data
register is empty.
46.4.2 Master Mode
The LPI2C master logic operates independently from the slave logic to perform all
master mode transfers on the I2C bus.
46.4.2.1 Transmit and Command FIFO commands
The transmit FIFO stores command data to initiate the various I2C operations. The
following operations can be initiated through commands in the transmit FIFO:
• START or Repeated START condition with address byte and expecting ACK or
NACK.
• Transmit data (this is the default for zero extended byte writes to the transmit FIFO).
Chapter 46 Low Power Inter-Integrated Circuit (LPI2C)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1455