NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 159 / 1761

Chapter 10
Port Control and Interrupts (PORT)
10.1 Chip-specific PORT information
Not all pin control settings mentioned in PORT_PCRn register are configurable for all
pins. Refer 'Bits Configurable' field in 'IO Signal Table' tab of IO Signal Description
Input Multiplexing sheet(s) attached to the Reference Manual. The bits apart from 'Bit
Configurable' fields are reserved and should not be varied from the reset values.
PCR bits corresponding to reset pad are non-sticky bits and on a functional reset, reset
functionality on this pin will be resumed. Prior to entering any ALT functionality, PCR of
corresponding pad should be properly configured.
On this chip, the pullup and pulldown enables are controllable in analog or disabled pin
muxing mode (corresponding to PORT_PCRn[MUX]=3’b000). Before entering Analog
mode (ALT0 corresponding to PORT_PCRn[MUX]=3'b000 for corresponding pads for
which Analog functionality is available), PUE and PUS should be configured as 0 in
corresponding PCR register.
PORT_PCRn[PFE] is configurable for only PTA5 and PTD3. See IO Signal Description
Input Multiplexing sheet(s) attached to the Reference Manual. PFE for these should be
configured in ALT7 mode only. For other modes, PFE should be kept 0.
The corresponding PAD should be configured for disabled mode(ALT0) prior to
configuring PORT_DFER register.
Any pad configuration done in RUN/VLPR mode is retained in low power
modes(STOP1,STOP2/VLPS).
Wait mode is not supported on this device.
See Module operation in available power modes for details on available power modes.
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 159