NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1066 / 1761

WINDOW
COUTA
COUT
CMPO
Minus input
Plus input
one filter
clock cycle
one filter
clock cycle
Figure 39-14. Windowed/Filtered mode operation
39.8 Memory map/register definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3000 CMP Control Register 0 (CMP0_C0) 32 R/W 0000_0000h 39.8.1/1066
4007_3004 CMP Control Register 1 (CMP0_C1) 32 R/W 0000_0000h 39.8.2/1070
4007_3008 CMP Control Register 2 (CMP0_C2) 32 R/W 0000_0000h 39.8.3/1073
39.8.1 CMP Control Register 0 (CMPx_C0)
Access:
• Supervisor read/write
• User read/write
Memory map/register definitions
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1066 NXP Semiconductors