NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
1b - Allows the given access type to occur
5
M0PE
Bus Master 0 Process Identifier Enable
0b - Do not include the process identifier in the evaluation
1b - Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
4-3
M0SM
Bus Master 0 Supervisor Mode Access Control
Defines the access controls for bus master 0 in Supervisor mode.
00b - r/w/x; read, write and execute allowed
01b - r/x; read and execute allowed, but no write
10b - r/w; read and write allowed, but no execute
11b - Same as User mode defined in M0UM
2-0
M0UM
Bus Master 0 User Mode Access Control
Defines the access controls for bus master 0 in User mode. M0UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions. In M0UM[2:0]: M0UM[2] controls read
permissions, M0UM[1] controls write permissions, and M0UM[0] controls execute permissions. For each
bit:
0b - An attempted access of that mode may be terminated with an access error (if not allowed by
another descriptor) and the access not performed
1b - Allows the given access type to occur
13.5 Functional description
In this section, the functional operation of the MPU is detailed, including the operation of
the access evaluation macro and the handling of error-terminated bus cycles.
13.5.1 Access evaluation macro
The basic operation of the MPU is performed in the access evaluation macro, a hardware
structure replicated in the two-dimensional connection matrix. As shown in the following
figure, the access evaluation macro inputs the crossbar bus address phase signals and the
contents of a region descriptor (RGDn) and performs two major functions:
• Region hit determination
• Detection of an access protection violation
The following figure shows a functional block diagram.
Chapter 13 Memory Protection Unit (MPU)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 231