NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1466 / 1761

46.4.5 Peripheral Triggers
The connection of the LPI2C peripheral triggers to other peripherals depend upon the
specific device being used.
Table 46-13. LPI2C Triggers
Trigger Description
Master Output Trigger The LPI2C master generates an output trigger that can be connected to other peripherals on the
device. The master output trigger asserts on both a Repeated START or STOP condition, and the
master output trigger remains asserted for one cycle of the LPI2C functional clock divided by the
prescaler.
Slave Output Trigger The LPI2C slave generates an output trigger that can be connected to other peripherals on the
device. The slave output trigger asserts on both a Repeated START or STOP condition that occurs
after a slave address match, and the slave output trigger remains asserted until the next slave SCL
pin negation.
Input Trigger To control the start of a LPI2C bus transfer, the LPI2C input trigger can be selected instead of the
HREQ input. The input trigger is synchronized and to be detected, the input trigger must assert for
at least 2 cycles of the LPI2C functional clock divided by the PRESCALE configuration. When the
LPI2C is busy, the HREQ input (and therefore the input trigger) is ignored.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1466 NXP Semiconductors