NXP Semiconductors MWCT101 S Series, Reference Manual

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4. Per 128-bit for Program Flash (bank 0), accessing the fifth longword requires 1 core
clock cycle. The flash memory read itself takes 4 clocks, but the access starts
immediately after the first read. As a result, 3 clocks for this access overlap with the
second, third, and fourth longword reads from the core.
5. Per 64-bit for Data Flash (bank 1), reading the fourth longword, like the second
longword, takes only 1 clock due to the 64-bit flash memory data bus.
6. Per 128-bit for Program Flash (bank 0), reading the sixth, seventh, and eighth
longwords takes only 1 clock each because the data is already available inside the
FMC.
31.6 Initialization and application information
The FMC does not require user initialization. Flash acceleration features are enabled by
default.
Chapter 31 Flash Memory Controller (FMC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 695