NXP Semiconductors MWCT101 S Series, Reference Manual

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17.4.1.18.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LK
0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
SEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.4.1.18.4 Fields
Field Function
31
LK
TRGMUX register lock.
This bit shows whether the register can be written or not. The LK bit can only be written once after any
system reset. Once LK is set, the SELx bits in this TRGMUX register cannot be changed until the next
system reset clears LK.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
—
This read-only bit field is reserved and always has the value 0.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
—
This read-only bit field is reserved and always has the value 0.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
—
This read-only bit field is reserved and always has the value 0.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. For the field
setting definitions, see
Memory map and register definition .
17.4.1.19 TRGMUX LPSPI0 Register (LPSPI0)
Chapter 17 Trigger MUX Control (TRGMUX)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 405