NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 943 / 1761

35.3 Memory map and register descriptions
Information about the registers related to the system mode controller can be found here.
Different SMC registers reset on different reset types. Each register's description provides
details. For more information about the types of reset on this chip, refer to the Reset
section details.
NOTE
The SMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
NOTE
Before executing the WFI instruction, the last register written to
must be read back. This ensures that all register writes
associated with setting up the low power mode being entered
have completed before the MCU enters the low power mode.
Failure to do this may result in the low power mode not being
entered correctly.
SMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_E000 SMC Version ID Register (SMC_VERID) 32 R 0100_0000h 35.3.1/943
4007_E004 SMC Parameter Register (SMC_PARAM) 32 R See section 35.3.2/944
4007_E008 Power Mode Protection register (SMC_PMPROT) 32 R/W 0000_0000h 35.3.3/945
4007_E00C Power Mode Control register (SMC_PMCTRL) 32 R/W 0000_0000h 35.3.4/947
4007_E010 Stop Control Register (SMC_STOPCTRL) 32 R/W 0000_0003h 35.3.5/949
4007_E014 Power Mode Status register (SMC_PMSTAT) 32 R 0000_0001h 35.3.6/950
35.3.1 SMC Version ID Register (SMC_VERID)
Address: 4007_E000h base + 0h offset = 4007_E000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MAJOR MINOR FEATURE
W
Reset
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 35 System Mode Controller (SMC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 943