NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1437 / 1761

• An 8-bit write to the DATA field will zero extend the CMD field, unless the CMD
field has been written separately since the last FIFO write; it (the 8-bit write) also
increments the FIFO write pointer.
• A 16-bit or 32-bit will write both the CMD and DATA fields and increment the
FIFO.
46.3.1.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
W CMD DATA
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
46.3.1.17.4 Fields
Field Function
31-11
—
Reserved
10-8
CMD
Command Data
000b - Transmit DATA[7:0]
001b - Receive (DATA[7:0] + 1) bytes
010b - Generate STOP condition
011b - Receive and discard (DATA[7:0] + 1) bytes
100b - Generate (repeated) START and transmit address in DATA[7:0]
101b - Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a
NACK to be returned.
110b - Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
111b - Generate (repeated) START and transmit address in DATA[7:0] using high speed mode.
This transfer expects a NACK to be returned.
7-0
DATA
Transmit Data
Performing an 8-bit write to DATA will zero extend the CMD field.
46.3.1.18 Master Receive Data Register (MRDR)
Chapter 46 Low Power Inter-Integrated Circuit (LPI2C)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1437