NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 285 / 1761

Chapter 15
Direct Memory Access Multiplexer (DMAMUX)
Chip-specific DMAMUX information
15.1.1 Number of channels
The number of channels across WCT101xS series varies across variants. See below table
for the same.
Table 15-1. Number of channles
Chips Number of channels
WCT1014S 16
WCT1015S 16
WCT1016S 16
15.1.2 DMA transfers via TRGMUX trigger
The triggers from TRGMUX module can trigger a DMA transfer on the first four DMA
channels, for example, the LPIT can trigger DMA via TRGMUX. See
Figure 17-2 for
module interconnectivity details. The LPIT/DMA periodic trigger assignments are
detailed at
LPIT/DMA Periodic Trigger Assignments.
Asynchronous DMA operation does not support trigger options.
In cases where multiple DMA request are routed to DMAMUX source, software needs to
make sure that only one DMA request is enabled at a time.
15.2 Introduction
15.1
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 285