NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 50-2. Debug components description (continued)
Module Description
The FPB also contains six instruction comparators for matching against
instruction fetches from Code space, and remapping to a corresponding
area in System space. Alternatively, the six instruction comparators can
individually configure the comparators to return a Breakpoint Instruction
(BKPT) to the processor core on a match, providing hardware breakpoint
capability.
Breakpoint and Watchpoint unit 2 hardware breakpoints available
TPIU (Trace Port Inteface Unit) Asynchronous Mode (1-pin) = TRACE_SWO (available on JTAG_TDO).
Supports 4 pin trace output and a single pin SWO
50.2 CM4 ROM table
The ROM table is used to hold the information about the debug components.
Table 50-3. Bit assignments in the ROM table
Bits Name Description
[31:12] Address offset Base address of the component, relative to the ROM address. Negative values are
permitted using two's complement.
ComponentAddress = ROMA (AddressOffset SHL 12).
[11:2] - Reserved SBZ.
[1] Format 1 = 32-bit format. In the DAP Debug ROM this is set to 1.
0 = 8-bit format.
[0] Entry present Set HIGH to indicate an entry is present.
Table 50-4. CM4 ROM table
Component Base address
SCS 0xE000E000
DWT 0xE0001000
FPB 0xE0002000
ITM 0xE0000000
TPIU + SWO 0xE0040000
ETM
1
0xE0041000
1. Present in WCT1016S variant only
Chapter 50 Debug
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1715