NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1217 / 1761

• MCOMBINE = 1
• COMBINE = 1, and
• CPWMS = 0
The Modified Combine PWM mode is intended to support the generation of PWM
signals where the period is not modified while the signal is being generated, but the duty
cycle will be varied. In this mode, an even channel (n) and adjacent odd channel (n+1)
are combined to generate a PWM signal in the channel (n) output. Thus, the channel (n)
match edge is fixed and the channel (n+1) match edge can be varied.
When a pair of channels is in Modified Combine PWM mode, it is recommend that the
other pairs also be in Modified Combine PWM mode.
In the Modified Combine PWM mode, assuming that CNTIN ≥ 0, MOD > 0, and CNTIN
< MOD:
• The PWM period is determined by (MOD - CNTIN + 0x0001);
• The channel (n) PWM duty cycle is calculated according to the following table.
Table 41-8. Modified Combine PWM Mode - Duty Cycles
Channel (n) PWM Duty Cycle Condition
0% duty cycle For CNTIN ≤ (C(n)V and C(n+1)V) ≤ MOD: C(n)V = C(n+1)V
duty cyle between 0% and 100% For CNTIN ≤ (C(n)V and C(n+1)V) ≤ MOD:
• if (C(n)V < C(n+1)V), then the duty cycle is (C(n+1)V -
C(n)V)
• if (C(n)V > C(n+1)V), then the duty cycle is [(MOD -
C(n)V) + (C(n+1)V - CNTIN) + 1]
100% duty cyle CNTIN ≤ C(n)V ≤ MOD and C(n+1)V > MOD
The channel (n) CHF bit is set and its interrupt is generated, if channel (n) CHIE = 1, at
the channel (n) match (FTM counter = C(n)V). The channel (n+1) CHF bit is set and its
interrupt is generated, if channel (n+1) CHIE = 1, at the channel (n+1) match (FTM
counter = C(n+1)V).
If channel (n) ELSB:ELSA = 1:0, then the channel (n) output is forced high at the
channel (n) match (FTM counter = C(n)V) and it is forced low at the channel (n+1)
match (FTM counter = C(n+1)V).
If channel (n) ELSB:ELSA = X:1, then the channel (n) output is forced low at the
channel (n) match (FTM counter = C(n)V) and it is forced high at the channel (n+1)
match (FTM counter = C(n+1)V).
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1217