NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1594 / 1761

NOTE
See Fault confinement in the CAN Protocol standard (ISO
11898-1) for details.
49.4.2.9.3 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BIT1ERR_FAS T BIT0ERR_FAS T
0
CRCERR_FAS T FRMERR_FAS T
STFERR_FAS T
0
ERROV R
ERRINT_FAS T
BOFFDONEINT
SYNCH
TWRNINT RWRNINT
W
W1C W1C W1C W1C W1C
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BIT1ER R BIT0ER R ACKERR CRCER R FRMER R
STFER R TXWRN RXWRN
IDL E
TX
FLTCONF
R X
BOFFINT
ERRIN T
0
W
W1C W1C
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
49.4.2.9.4 Fields
Field Function
31
BIT1ERR_FAST
Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
This bit indicates when an inconsistency occurs between the transmitted and the received bit in the data
phase of CAN FD frames with the BRS bit set.
0b - No such occurrence.
1b - At least one bit sent as recessive is received as dominant.
30
BIT0ERR_FAST
Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
This bit indicates when an inconsistency occurs between the transmitted and the received bit in the data
phase of CAN FD frames with the BRS bit set.
0b - No such occurrence.
1b - At least one bit sent as dominant is received as recessive.
29
—
Reserved
28
CRCERR_FAST
Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
This bit indicates that a CRC error has been detected by the receiver node in the CRC field of CAN FD
frames with the BRS bit set, that is, the calculated CRC is different from the received.
0b - No such occurrence.
1b - A CRC error occurred since last read of this register.
Table continues on the next page...
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1594 NXP Semiconductors