NXP Semiconductors MWCT101 S Series, Reference Manual

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Backup reset becomes valid when interrupt is enabled and the watchdog clock is from
non bus clock. If interrupt is enabled, once the bus clock is cut off before exiting interrupt
routine, the normal watchdog reset will be blocked. Under this case, the second overflow
will cause backup reset directly.
21.4.6 Functionality in debug and low-power modes
By default, the watchdog is not functional in Debug mode, Wait mode, or Stop mode.
However, the watchdog can remain functional in these modes as follows:
• For Debug mode, set CS[DBG]. (This way the watchdog is functional in Debug
mode even when the CPU is held by the Debug module.)
• For Wait mode, set CS[WAIT].
• For Stop mode, set CS[STOP], CS[WAIT], and ensure the clock source is active in
Stop mode.
NOTE
The watchdog can generate interrupt in Stop mode.
For Debug mode and Stop mode, in addition to the above
configurations, a clock source other than the bus clock must be
used as the reference clock for the counter; otherwise, the
watchdog cannot function.
21.4.7 Fast testing of the watchdog
Before executing application code in safety critical applications, users are required to test
that the watchdog works as expected and resets the MCU. Testing every bit of a 16-bit
counter by letting it run to the overflow value takes a relatively long time (64 k clocks).
To help minimize the startup delay for application code after reset, the watchdog has a
feature to test the watchdog more quickly by splitting the counter into its constituent
byte-wide stages. The low and high bytes are run independently and tested for timeout
against the corresponding byte of the timeout value register. (For complete coverage
when testing the high byte of the counter, the test feature feeds the input clock via the 8th
bit of the low byte, thus ensuring that the overflow connection from the low byte to the
high byte is tested.)
Using this test feature reduces the test time to 512 clocks (not including overhead, such as
user configuration and reset vector fetches). To further speed testing, use a faster clock
(such as the bus clock) for the counter reference.
Configuring the Watchdog
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
468 NXP Semiconductors