NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 475 / 1761

22.3.1.1 CRC Memory map
CRC base address: 4003_2000h
Offset Register Width
(In bits)
Access Reset value
0h CRC Data register (DATA) 32 RW FFFF_FFFFh
4h CRC Polynomial register (GPOLY) 32 RW 0000_1021h
8h CRC Control register (CTRL) 32 RW 0000_0000h
22.3.1.2 CRC Data register (DATA)
22.3.1.2.1 Offset
Register Offset
DATA 0h
22.3.1.2.2 Function
The CRC Data register contains the value of the seed, data, and checksum. When
CTRL[WAS] is set, any write to the data register is regarded as the seed value. When
CTRL[WAS] is cleared, any write to the data register is regarded as data for general CRC
computation.
In 16-bit CRC mode, the HU and HL fields are not used for programming the seed value,
and reads of these fields return an indeterminate value. In 32-bit CRC mode, all fields are
used for programming the seed value.
When programming data values, the values can be written 8 bits, 16 bits, or 32 bits at a
time, provided all bytes are contiguous; with MSB of data value written first.
After all data values are written, the CRC result can be read from this data register. In 16-
bit CRC mode, the CRC result is available in the LU and LL fields. In 32-bit CRC mode,
all fields contain the result. Reads of this register at any time return the intermediate CRC
value, provided the CRC module is configured.
Chapter 22 Cyclic Redundancy Check (CRC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 475