NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1139 / 1761

41.4.3.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CHOV
CHIS
TRIGMODE
CHF
CHIE
MSB
MSA ELS B ELS A
ICRST
DMA
W
0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
41.4.3.5.4 Fields
Field Function
31-11
—
Reserved
10
CHOV
Channel (n) Output Value
The CHOV bit has the final value of the channel (n) output.
NOTE: The CHOV bit should be ignored when the channel (n) is not in an output mode.
0b - The channel (n) output is zero.
1b - The channel (n) output is one.
9
CHIS
Channel (n) Input State
The CHIS bit has the value of the channel (n) input after the double-sampling or the filtering (if the
channel (n) filter is enabled) both them are inside the FTM.
NOTE: The CHIS bit should be ignored when the channel (n) is not in an input mode.
NOTE: When the pair channels is on dual edge mode, the channel (n+1) CHIS bit is the channel (n+1)
input value and not the channel (n) input value (this signal is the input signal used by the dual
edge mode).
0b - The channel (n) input is zero.
1b - The channel (n) input is one.
8
TRIGMODE
Trigger mode control
This bit controls the trigger generation on FTM channel outputs. This mode is allowed only if when FTM
channel is configured to EPWM or CPWM modes. If a match in the channel occurs, a trigger pulse with
one FTM clock cycle width will be generated in the channel output. See
Channel trigger output .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0b - Channel outputs will generate the normal PWM outputs without generating a pulse.
1b - If a match in the channel occurs, a trigger generation on channel output will happen. The
trigger pulse width has one FTM clock cycle.
7
CHF
Channel (n) Flag
Set by hardware when an event occurs on the channel (n). CHF is cleared by reading the CnSC register
while CHF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
Table continues on the next page...
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1139