NXP Semiconductors MWCT101 S Series, Reference Manual

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10.1.1 Number of PCRs
The number of PCRs for each PORT varies across the products in the WCT101xS series.
The following table shows the number of PCRs for each PORT on each product.
Memory
map and register definition documents the superset number of implemented ports. PCR
registers corresponding to ports to ports which are not present in particular device are
read only 0. See RM attachments IO Signal Description Input Multiplexing sheet(s) for
details on the count of PCRs on each product.
Table 10-1. PCRs on each product
PORT
Number of PCRs
1
WCT1014S WCT1015S WCT1016S
PORT A 18 25 32
PORT B 18 27 32
PORT C 18 25 32
PORT D 18 27 32
PORT E 17 24 28
1. See the attachment MWCT101xS_IO_Signal_Description_Input_Multiplexing.xlsx for details.
10.1.2 Finding address for PORTx_PCRn
For example, in order to write to the PORT register of PTC3 (PTxn), the corresponding
mapped register is PORTC_PCR3 (PORTx_PCRn):
• To find PORTC base address, look up the 'Start address' of "Port C" in "Peripheral
Memory Map" tab in the attached WCT101xS_Memory_Map.xls. This is referred
henceforth as PORTC_Base_address.
• To reach PCRn, refer to address 'PORTx_Base_a n*4d'. For PCR3 of
PORTC, this refers to 'PORTC_Base_a 3*4d'. The attached IO Signal
Description Input Muxing sheet(s) for each device provides the fields available in
PCR per PORTx_PCRn (For each PTxn pin) in the tab IO Signal Table.
10.1.3 I/O configuration sequence
1. Ensure pins for the peripheral are in tristate sate (default out of reset).
2. Initialize peripheral clock in the Peripheral Clock Controller register(PCC) and
peripheral specific clocking configurations.
3. Configure the peripheral
4. Initialize port clock for the peripheral pins in the Peripheral Clock Controller register
(PCC_PORTx).
Chip-specific PORT information
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
160 NXP Semiconductors