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33.8.2.4 IP Bus and AHB Access Command Collisions
There are two flags related to this topic, the QSPI_FR[IPAEF] and QSPI_FR[IPIEF].
Refer to sub-section "Reading Serial Flash Data into the QuadSPI Module" of
section, for a description of the flags.
33.8.3 Flash Device Selection
Regardless of the SFM Command (IP or AHB) the access mode is selected by specifying
the 32 bit address value for the following SFM Command.
For IP Commands the access mode is selected with the address programmed into the
QSPI_SFAR register. Refer to
Serial Flash Address Register (QuadSPI_SFAR)
details.
For AHB Commands the access mode is determined by the memory mapped address
which is accessed Refer to
for details.
33.8.4 DMA Usage
For the complete description of the DMA module refer to the related DMA Controller
chapter. In this paragraph only the details specific to the DMA usage related to the
QuadSPI module are given.
33.8.4.1 DMA Usage in Normal Mode
33.8.4.1.1 Bandwidth considerations
Careful consideration of the throughput rate of the entire chain (serial flash -> AHB bus /
IP Bus -> DMA controller) involved in the read/write data process is essential for proper
operation. Such analysis must take into account not only the data rate provided by the
serial flash but also the data rate of the AHB bus and the performance of the DMA
controller in reading/writing data from/to the RX/TX buffer.
Two figures must match for proper operation, that means that the data rate provided by
the serial flash device must not exceed the average RX Buffer readout data rate.
Otherwise, the longer this state persists, a RX Buffer overflow will result. Similarly, the
data consumed by the serial flash device must not exceed the average TX buffer fill rate.
If this persists, it would eventually lead to an underrun.
AHB Bus Side (data read):
Initialization/Application Information
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
908
NXP Semiconductors
Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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