If the associated error was detected in the received character that caused STAT[RDRF] to
be set, the error flags - noise flag (STAT[NF]), framing error (STAT[FE]), and parity
error flag (STAT[PF]) - are set at the same time as STAT[RDRF]. These flags are not set
in overrun cases.
If STAT[RDRF] was already set when a new character is ready to be transferred from the
receive shifter to the receive data buffer, the overrun (STAT[OR]) flag is set instead of
the data along with any associated NF, FE, or PF condition is lost.
If the received character matches the contents of MATCH[MA1] and/or MATCH[MA2]
then the STAT[MA1F] and/or STAT[MA2F] flags are set at the same time that
STAT[RDRF] is set.
At any time, an active edge on the RXD serial data input pin causes the
STAT[RXEDGIF] flag to set. The STAT[RXEDGIF] flag is cleared by writing a 1 to it.
This function depends on the receiver being enabled (CTRL[RE] = 1).
47.4.8 Peripheral Triggers
The connection of the LPUART peripheral triggers with other peripherals are device
specific.
47.4.8.1 Output Triggers
The LPUART generates three output triggers that can be connected to other peripherals
on the device.
• The transmit word trigger asserts at the end of each transmitted word, it negates after
one bit period.
• The receive word trigger asserts at the end of each received word that is written to
the receive FIFO, for one oversampling clock period.
• The receive idle trigger asserts at when the idle flag would set, for one oversampling
clock period.
47.4.8.2 Input Trigger
The LPUART supports one peripheral input trigger, that can be configured in one of the
following ways.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
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Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
Page 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1514: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1514 NXP Semiconductors...
Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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