NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1313 / 1761

42.4.1.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
TMR_VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TMR_VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
42.4.1.9.4 Fields
Field Function
31-0
TMR_VAL
Timer Value
• In compare mode: Timer Value (TMR_VAL) is the timer channel start value.
• The timer will count down until the timer reaches 0, then the timer will generate an interrupt
and load the Timer Value register (TVAL n ) value again.
• Writing a new value to the Timer Value register (TVAL n ) will not restart the timer channel;
instead the new value will be loaded after the timer expires .
• To abort the current timer cycle and start a timer period with a new value, the timer channel
must be disabled and enabled again .
• In capture mode: whenever the trigger asserts, the Timer Value register stores the inverse of the
counter value.
00000000000000000000000000000000b - Invalid load value in compare mode
00000000000000000000000000000001b - Invalid load value in compare mode
00000000000000000000000000000010-11111111111111111111111111111111b - In compare
mode: the value to be loaded; in capture mode, the value of the timer
42.4.1.10 Current Timer Value (CVAL0 - CVAL3)
42.4.1.10.1 Offset
Register Offset
CVAL0 24h
CVAL1 34h
CVAL2 44h
CVAL3 54h
Chapter 42 Low Power Interrupt Timer (LPIT)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1313