NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1723 / 1761

4. Global system timestamping: Timestamps can optionally be generated using a
system-wide 48-bit count value.
50.10 Core trace connectivity
Following table provides Core trace connectivity across WCT101xS devices.
Table 50-10. WCT101xS Core Trace Connectivity
Chip Feature
WCT1014S, WCT1015S DWT and ITM trace data can traced out only through SWO
interface.
WCT1016S DWT, ETM and ITM trace data can be traced out through
SWO or 4 pin parallel trace port.
50.11 TPIU
The TPIU is a trace data drain that acts as a bridge between the on-chip tracedata to a
data stream that is captured by a Trace Port Analyzer (TPA).
Table 50-11. WCT101xS TPIU
Chip Feature
WCT1014S, WCT1015S The TPIU in the device supports a limited subset of the full
TPIU functionality (only SWO mode), to minimize gatecount
for a simple debug solution.
WCT1016S For applications which require high trace bandwidth, 4 pin
trace interface can be used.
SWO mode can be used only in SWD mode as it uses the
same pin as JTAG TDO.
Maximum trace clock for SWO is 20 MHz. Maximum trace clock for 4-pin trace
interface mapped to:
• Fast pads is 80 MHz
• Slow pads is 20 MHz
This can be configured through System Clock Divider Register 4 (CLKDIV4) register.
Chapter 50 Debug
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1723