NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 964 / 1761

36.6.1 PMC register descriptions
NOTE
Different portions of PMC registers are reset only by particular
reset types. Each register's description provides details.
NOTE
The PMC registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
36.6.1.1 PMC Memory map
PMC base address: 4007_D000h
Offset Register Width
(In bits)
Access Reset value
0h Low Voltage Detect Status and Control 1 Register (LVDSC1) 8 RW Table 36-
1h Low Voltage Detect Status and Control 2 Register (LVDSC2) 8 RW 00h
2h Regulator Status and Control Register (REGSC) 8 RW Table 36-
4h Low Power Oscillator Trim Register (LPOTRIM) 8 RW Table 36-1
36.6.1.2 Low Voltage Detect Status and Control 1 Register (LVDSC1)
36.6.1.2.1 Offset
Register Offset
LVDSC1 0h
36.6.1.2.2 Function
This register contains status and control bits to support the low voltage detect function.
NOTE
When the internal voltage regulator is in lowe power mode, the
LVD system is disabled, regardless of the PMC_LVDSC1
settings.
Memory Map and Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
964 NXP Semiconductors