NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1468 / 1761

47.2 Introduction
47.2.1 Features
Features of the LPUART module include:
• Full-duplex, standard non-return-to-zero (NRZ) format
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock:
• Baud rate can be configured independently of the bus clock frequency
• Supports operation in Stop modes
• Interrupt, DMA or polled operation:
• Transmit data register empty and transmission complete
• Receive data register full
• Receive overrun, parity error, framing error, and noise error
• Idle receiver detect
• Active edge on receive pin
• Break detect supporting LIN
• Receive data match
• Hardware parity generation and checking
• Programmable 7-bit, 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods:
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
• Hardware flow control support for request to send (RTS) and clear to send (CTS)
signals
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1468 NXP Semiconductors