NXP Semiconductors MWCT101 S Series, Reference Manual

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Register Offset
TCDn_SLAST 100Ch + (n × 20h)
16.4.5.25.2 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SLAST
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLAST
W
Reset
u u u u u u u u u u u u u u u u
16.4.5.25.3 Fields
Field Function
31-0
SLAST
Last Source Address Adjustment
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
This register uses two's complement notation; the overflow bit is discarded.
16.4.5.26 TCD Destination Address (TCD0_DADDR - TCD15_DADDR)
16.4.5.26.1 Offset
For n = 0 to 15:
Register Offset
TCDn_DADDR 1010h + (n × 20h)
16.4.5.26.2 Function
This register contains the destination address of the transfer.
Chapter 16 Enhanced Direct Memory Access (eDMA)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 341