NXP Semiconductors MWCT101 S Series, Reference Manual

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end
begin
= 1
= 0
end
end
end
end
end
= 1
= 0
= 1
= 1
= 0
= 0
= 1
INVCTRL is updated
by software trigger
software
trigger
hardware
trigger
INVCTRL is updated
by hardware trigger
enhanced PWM synchronization
update INVCTRL register by
PWM synchronization
update INVCTRL register at
each rising edge of FTM input clock
= yes
0 =
1 =
0 =
0 =
no =
1 =
INVC
bit ?
SYNCMODE
bit ?
rising edge
of FTM input
clock ?
update INVCTRL
with its buffer value
update INVCTRL
with its buffer value
HWINVC
bit ?
TRIGn
bit ?
wait hardware trigger n
update INVCTRL
with its buffer value
HWTRIGMODE
bit ?
clear TRIGn bit
SWINVC
bit ?
SWSYNC
bit ?
Figure 41-65. INVCTRL register synchronization flowchart
41.5.13.9 SWOCTRL register synchronization
The SWOCTRL register synchronization updates the SWOCTRL register with its buffer
value.
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1233