NXP Semiconductors MWCT101 S Series, Reference Manual

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SCG_FIRCCSR field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
FIRCERR
Fast IRC Clock Error
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one
0 Error not detected with the Fast IRC trimming.
1 Error detected with the Fast IRC trimming.
25
FIRCSEL
Fast IRC Selected status
0 Fast IRC is not the system clock source
1 Fast IRC is the system clock source
24
FIRCVLD
Fast IRC Valid status
0 Fast IRC is not enabled or clock is not valid.
1 Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the
FIRC analog.
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–8
Reserved
This field is reserved.
This field is reserved. Software should write 0 to these bits to maintain compatibility.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
FIRCREGOFF
Fast IRC Regulator Enable
0 Fast IRC Regulator is enabled.
1 Fast IRC Regulator is disabled.
2–1
Reserved
This field is reserved. Software should write 0 to these bits to maintain compatibility.
This field is reserved.
0
FIRCEN
Fast IRC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
0 Fast IRC is disabled
1 Fast IRC is enabled
Memory Map/Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
554 NXP Semiconductors