NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1464 / 1761

Table 46-11. Master Interrupts and DMA Requests
Master Status Register
(MSR)
Description Can generate
Flag Name Interrupt? DMA
Request?
Low Power
Wakeup?
TDF Transmit Data
Flag
Data can be written to Transmit FIFO, as
configured by the Transmit FIFO Watermark
MFCR[TXWATER] Y TX Y
RDF Receive Data
Flag
Data can be read from the Receive FIFO, as
configured by the Receive FIFO Watermark
MFCR[RXWATER] Y RX Y
EPF End Packet
Flag
Master has transmitted a Repeated START or
STOP condition Y N Y
SDF STOP Detect
Flag
Master has transmitted a STOP condition Y N Y
NDF NACK Detect
Flag
• During an address byte, the master
expected an ACK but detected a NACK
• During an address byte, the master
expected a NACK but detected an ACK
• During a master-transmitter data byte,
the master detected a NACK
Y N Y
ALF Arbitration
Lost Flag
• The master lost arbitration due to a
START/STOP condition detected at the
wrong time
• Or the master was transmitting data but
received different data than the data
that was transmitted
Y N Y
FEF FIFO Error
Flag
The master is expecting a START condition in
the Command FIFO, but the next entry in the
Command FIFO is not a START condition Y N Y
PLTF Pin Low
Timeout Flag
Pin low timeout is enabled and SCL (or SDA if
configured) is low for longer than the
configured timeout Y N Y
DMF Data Match
Flag
The received data matches the configured
data match, but the received data is not
discarded due to a command FIFO entry Y N Y
MBF Master Busy
Flag
LPI2C master is busy transmitting/receiving
data N N N
BBF Bus Busy Flag LPI2C master is enabled and activity is
detected on I2C bus, but a STOP condition
has not been detected and a bus idle timeout
(if enabled) has not occurred.
N N N
46.4.4.2 Slave mode
The next table lists the slave mode sources that can generate LPI2C slave interrupts and
the LPI2C slave transmit/receive DMA requests.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1464 NXP Semiconductors