NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 859 / 1761

Address: 4007_6000h base + 154h offset = 4007_6154h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QuadSPI_TBDR field descriptions
Field Description
TXDATA TX Data
On write access the data is written into the next available entry of the TX Buffer and the
QPSI_TBSR[TRBFL] field is updated accordingly.
On a read access, the last data written to the register is returned.
33.4.2.20 Tx Buffer Control Register (QuadSPI_TBCT)
This register contains control information for transmit data buffer.
Address: 4007_6000h base + 158h offset = 4007_6158h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved WMRK
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QuadSPI_TBCT field descriptions
Field Description
31–5
Reserved
This field is reserved.
WMRK Determines the watermark for the TX Buffer. When the number of available space in TX Buffer is greater
than the number given by (WMRK+1), QSPI_SR[TXWA] is asserted. The values should be entered as the
number of 4Bytes entries minus 1. For example, a value of 0x0 would set the watermark to 4 bytes, 1 to 8
bytes, 2 to 12 Bytes, and so on.For details, refer to
DMA Usage .
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 859