NXP Semiconductors MWCT101 S Series, Reference Manual

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MCM_LMFDLR field descriptions
Field Description
PEFDL Parity or ECC Fault Data Low
8.4 Functional description
This section describes the functional description of MCM module.
8.4.1 Interrupts
The MCM interrupt is generated if any of the following is true:
• FPU input denormal interrupt is enabled (FIDCE) and an input is denormalized
(FIDC)
• FPU inexact interrupt is enabled (FIXCE) and a number is inexact (FIXC)
• FPU underflow interrupt is enabled (FUFCE) and an underflow occurs (FUFC)
• FPU overflow interrupt is enabled (FOFCE) and an overflow occurs (FOFC)
• FPU divide-by-zero interrupt is enabled (FDZCE) and a divide-by-zero occurs
(FDZC)
• FPU invalid operation interrupt is enabled (FIOCE) and an invalid occurs (FIOC)
• SRAM_L correctable (1-bit) ECC error
• SRAM_L uncorrectable ECC error
• SRAM_U correctable (1-bit) ECC error
• SRAM_U uncorrectable ECC error
• PC data parity error
• PC tag parity error
• Cache write buffer error
8.4.1.1 Determining source of the interrupt
These steps can be used to determine the exact source of the interrupt:
1. Logical AND the interrupt status flags with the corresponding interrupt enable bits:
ISCR[31:16] and ISCR[15:0].
2. Search the result for asserted bits which indicate the exact interrupt sources.
NOTE
ECC and Parity interrupts are determined by LMPECR
(interrupt enable) and LMPEIR (interrupt source).
Chapter 8 Miscellaneous Control Module (MCM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 129