NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1710 / 1761

• Error
• Error Fast
• Tx Warning
• Rx Warning
The Bus Off, Error, Tx Warning, and Rx Warning interrupt mask bits are located in the
CTRL1 register.
The interrupt sources for Pretended Networking (Wake up by Match Flag and Wake up
by Timeout Flag) can be read in the WU_MTC register and the respective interrupt mask
bits are located in CTRL1_PN register.
49.5.13 Bus interface
CPU access to FlexCAN registers is subject to the following rules:
• Unrestricted read and write access to supervisor registers (registers identified with
S/U in Table 49-5 in Supervisor Mode or with S only) results in an access error.
• Read and write access to implemented reserved address space results in an access
error.
• Write access to positions whose bits are all currently read-only results in an access
error. If at least one of the bits is not read-only then no access error is issued. Write
permission to positions or some of their bits can change depending on the mode of
operation or transitory state. See register and field descriptions for details.
• Read and write access to unimplemented address space results in access error.
• Read and write access to RAM located positions during Low Power mode results in
an access error.
• It is possible for the RXIMR memory region to be considered as general purpose
memory and available for access. There are two ways of doing this:
a. If MCR[IRMQ] is cleared, the individual masks (RXIMR) are disabled. In this
case the RXIMR memory region is considered as general purpose memory.
b. If MCR[MAXMB] is programmed with a value smaller than the available
number of MBs, then the unused memory space can be used as general purpose
RAM space. Note that reserved words within RAM cannot be used. As an
example, suppose FlexCAN's RAM can support up to 16 MBs, CTRL2[RFFN]
is 0x0, and MCR[MAXMB] is programmed with zero. The maximum number of
MBs in this case becomes one. The RAM starts at 0x0080, and the space from
0x0080 to 0x008F is used by the one MB. The memory space from 0x0090 to
0x017F is available. The space between 0x0180 and 0x087F is reserved. The
space from 0x0880 to 0x0883 is used by the one individual mask and the
available memory in the mask registers space would be from 0x0884 to 0x08BF.
From 0x08C0 through 0x09DF there are reserved words for internal use which
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1710 NXP Semiconductors