NXP Semiconductors MWCT101 S Series, Reference Manual

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• Receive 1-256 bytes of data (can also be configured to discard receive data and not
store in receive FIFO).
• STOP condition (can also be configured to send STOP condition when transmit FIFO
is empty).
Multiple transmit and receive commands can be inserted between the START condition
and STOP conditon; transmit and receive commands must not be interleaved (to comply
with the I2C specification). The receive data command and the receive data and discard
commands can be interleaved, to ensure that only the desired received data is stored in
the receive FIFO (or compared with the data match logic).
The LPI2C master will automatically transmit a NACK on the last byte of a receive data
command unless the next command in the FIFO is also a receive data command. A
NACK is also automatically transmitted if the transmit FIFO is empty when a receive
data command completes.
The LPI2C master supports 10-bit addressing through a (repeated) START condition,
followed by a transmit data byte containing the second address byte, followed by any
number of data bytes with the master-transmit data.
A START or Repeated START condition that is expecting a NACK (for example,HS-
mode master code) must be followed by a STOP or (repeated) START condition.
46.4.2.2 Master operations
Whenever the LPI2C is enabled, it monitors the I2C bus to detect when the I2C bus is
idle (MSR[BBF]). The I2C bus is no longer considered idle if either SCL or SDA are
low, and the I2C bus becomes idle if a STOP condition is detected or if a bus idle timeout
is detected (as configured by MCFGR2[BUSIDLE]). After the I2C bus is idle, the
transmit FIFO is not empty, and the host request is either asserted or disabled, then the
LPI2C master will initiate a transfer on the I2C bus. This involves the following steps:
• Wait the bus idle time equal to (MCCR0[CLKLO] + 1) multiplied by the prescaler
(MCFGR1[PRESCALE]).
• Transmit a START condition and address byte using the timing configuration in the
Master Clock Configuration Register 0 (MCCR0); if a high speed mode transfer is
configured, then the timing configuration from Master Clock Configuration Register
1 (MCCR1) is used instead.
• Perform master-transmit or master-receive transfers, as configured by the transmit
FIFO.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1456 NXP Semiconductors