NXP Semiconductors MWCT101 S Series, Reference Manual

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26.3.15 Fast IRC Divide Register (SCG_FIRCDIV)
Changes to FIRCDIV should be done when FAST IRC is disabled to prevent glitches to
output divided clock.
Address: 4006_4000h base + 304h offset = 4006_4304h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
Reserved
0
FIRCDIV2
0
FIRCDIV1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_FIRCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
FIRCDIV2
Fast IRC Clock Divide 2
Clock divider 2 for the Fast IRC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FIRCDIV1 Fast IRC Clock Divide 1
Clock divider 1 for Fast IRC. Used to generate the clock source for modules that need an asynchronous
clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
Chapter 26 System Clock Generator (SCG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 555