NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 505 / 1761

RCM_SSRS field descriptions (continued)
Field Description
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
SLOL
Sticky Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the SCG PLL/FLL. See the SCG description for
information on the loss-of-lock event.
0 Reset not caused by a loss of lock in the PLL/FLL
1 Reset caused by a loss of lock in the PLL/FLL
2
SLOC
Sticky Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The SCG SOSC clock monitor must be
enabled for a loss of clock to be detected. Refer to the detailed SCG description for information on
enabling the clock monitor.
0 Reset not caused by a loss of external clock.
1 Reset caused by a loss of external clock.
1
SLVD
Sticky Low-Voltage Detect Reset
If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage, an LVD reset occurs.
This field is also set by POR.
0 Reset not caused by LVD trip or POR
1 Reset caused by LVD trip or POR
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24.4.6 System Reset Interrupt Enable Register (RCM_SRIE)
This register provides the option to delay the assertion of a system reset for a period of
time (DELAY field) while an interrupt is generated. When an interrupt for a reset source
is enabled, software has time to perform a graceful shutdown. A Chip POR source cannot
be delayed by this feature. The SRS updates only after the system reset occurs.
NOTE
The reset delay feature requires the LPO clock to remain active.
NOTE
This register is reset on Chip POR only, it is unaffected by
other reset types.
Chapter 24 Reset Control Module (RCM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 505