NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1337 / 1761

Table 43-2. Modes of operation (continued)
Modes Description
Stop
The LPTMR continues to operate normally and
can be configured to exit the low-power mode by
generating an interrupt request.
Low-Leakage
The LPTMR continues to operate normally and
can be configured to exit the low-power mode by
generating an interrupt request.
Debug
The LPTMR operates normally in Pulse Counter
mode, but the counter does not increment in
Time Counter mode.
43.3 LPTMR signal descriptions
Table 43-3. LPTMR signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input pin
43.3.1 Detailed signal descriptions
Table 43-4. LPTMR interface—detailed signal descriptions
Signal I/O Description
LPTMR_ALT n I Pulse Counter Input
The LPTMR can select one of the input pins to be used in Pulse Counter mode.
State meaning Assertion—If configured for pulse counter mode with
active-high input, then assertion causes the CNR to
increment.
Deassertion—If configured for pulse counter mode with
active-low input, then deassertion causes the CNR to
increment.
Timing Assertion or deassertion may occur at any time; input may
assert asynchronously to the bus clock.
43.4 Memory map and register definition
NOTE
The LPTMR registers are reset only on a POR or LVD event.
See
LPTMR power and reset for more details.
Chapter 43 Low Power Timer (LPTMR)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1337