NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 976 / 1761

NOTE
For the TRGMUX triggering, only up to 4 pre-triggers are
supported.
NOTE
Each PDB supports 4 slots/4 triggers channel, and each channel
supports 8 pre-triggers. The triggers of PDB channels can are
OR'ed together to support up to 32 pre-triggers if necessary.
PDB0 pulse out
PDB0 CH0 trigger
ADC0_SC1A:B[COCO]
TRGMUX_PDB0
63
••
•
1
0
out[15:12]
SIM_ADCOPT [ADC0PRETRGSEL]
SWTRG
PDB_SC[TRGSEL]
Channel 0
Channel 1
Pulse-out
Ch0
pretriggers[7:0]
out56
PDB0 Ch0
pretriggers[7:4]
PDB trigger
ACK[7:0]
ADHWTS I:P
ADC_SC1A:DD[COCO]
PDB0
TRGMUX_ADC0
63
••
•
1
0
Pretriggers[3:0]
Triggers[3:0]
in36
in34
in[31:30]
Ch0 trigger
Trigger_in0
Ch1
pretriggers[7:0]
Pulse-out
trigger
ACK[15:8]
Ch1 trigger
PDB0 Ch0 pretriggers[3:0]
PDB pretriggers[3:0]
TRGMUX pretriggers[3:0]
SIM_ADCOPT [ADC0TRGSEL]
TRGMUX triggers[3:0]
PDB trigger
ADHWTS E:H
ADHWTS A:D
ADHWT
SIM_ADCOPT [ADC0SWPRETRG]
Trigger Latching and Arbitration Unit*
* The block depicts simplified schematic and doesn’t show detailed latching. See section 'Trigger Latching and Arbitration' of ADC chapter for details
Channel 2
Channel 3
ADHWTS Y:DD
ADHWTS Q:X
ADC0
TRGMUX
ACK[31:24]
ACK[23:16]
Figure 37-2. ADC0_PDB0 ADC Triggering scheme example
ADC Trigger Sources
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
976 NXP Semiconductors