NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 547 / 1761

26.3.9 System OSC Divide Register (SCG_SOSCDIV)
The SCG_SOSCDIV register provides the control of 2 clock trees which can be used to
provide optional peripheral functional clocks, or alternative module clocks. Each clock
tree has optional dividers of the input SOSC clock. Changes to SOSCDIV should be done
when System OSC is disabled to prevent glitches to output divided clock.
Address: 4006_4000h base + 104h offset = 4006_4104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SOSCDIV2
0
SOSCDIV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SOSCDIV field descriptions
Field Description
31–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18–16
Reserved
This field is reserved.
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility.
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
SOSCDIV2
System OSC Clock Divide 2
Clock divider 2 for System OSC. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
SOSCDIV1 System OSC Clock Divide 1
Clock divider 1 for System OSC. Used to generate the clock source for modules that need an
asynchronous clock source.
000 Output disabled
Table continues on the next page...
Chapter 26 System Clock Generator (SCG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 547