NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 1457 / 1761

• Transmit NACK on the last byte of a master-receive transfer, unless the next
command in the transmit FIFO is also a receive data command and the transmit FIFO
is not empty.
• Transmit a Repeated START or STOP condition as configured by the transmit FIFO
and/or MCFGR1[AUTOSTOP]. A repeated START can change which timing
configuration register is used.
When the LPI2C master is disabled (either due to MCR[MEN] being clear or
automatically due to mode entry), the LPI2C will continue to empty the transmit FIFO
until a STOP condition is transmitted. However, the LPI2C will no longer stall the I2C
bus waiting for the transmit or receive FIFO, and after the transmit FIFO is empty, the
LPI2C will generate a STOP condition automatically.
The LPI2C master can stall the I2C bus under certain conditions; this will result in SCL
pulled low continuously on the first bit of a byte, until the condition is removed:
• LPI2C master is enabled and busy, the transmit FIFO is empty, and
MCFGR1[AUTOSTOP] is clear.
• LPI2C master is enabled and receiving data, receive data is not being discarded (due
to command or receive data match), and the receive FIFO is full.
46.4.2.3 Receive FIFO and Data Matching
The receive FIFO is used to store receive data during master-receiver transfers. Receive
data can also be configured to discard receive data instead of storing in the receive FIFO;
this is configured by the command word in the transmit FIFO.
Receive data supports a receive data match function that can match received data against
one of two bytes or against a masked data byte. The data match function can also be
configured to compare only the first one or two received data words since the last
(repeated) START condition. Receive data that is already discarded due to the command
word cannot cause the data match to set, and will delay the match on the first received
data word until after the discarded data is received. The receiver match function can also
be configured to discard all receive data until a data match is detected, using the
MCFGR0[RDMO] control bit. When clearing the MCFGR0[RDMO] control bit
following a data match, clear MCFGR0[RDMO] before clearing MSR[DMF], to allow
all subsequent data to be received.
Chapter 46 Low Power Inter-Integrated Circuit (LPI2C)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1457