NXP Semiconductors MWCT101 S Series, Reference Manual

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• Trigger Select (TRG_SEL) selects the input trigger for the channel from all of the
other channel's trigger outputs.
• Trigger Source (TRG_SRC) selects between the internal trigger and the external
trigger inputs to the channel.
The selected trigger affects how the timer operates, using the configuration of the TROT,
TSOI and TSOT bits.
Table 42-5. How bits control timer operations
If = Then
TSOI
Timer Stop On
Interrupt
1 then the counter stops on a Timer Interrupt flag (MSR[TIFn]) assertion. To reload and
decrement, it requires:
• a trigger (if TSOT = 1)
• a T_EN rising edge (if TSOT = 0)
0 then the counter does not stop after timeout
TROT
Timer Reload On
Trigger
1 then the counter is loaded on each trigger
0 then the counter is loaded on every T_EN rising edge or timeout rising edge (timeout not
used in Capture modes)
TSOT
Timer Start On
Trigger
1 then the counter will start to decrement on a trigger. Subsequent triggers are ignored until
the counter times out.
0 then the counter decrements immediately on the next clock edge. When channel is
Chained or in Capture mode, TSOT has no effect.
In different timer modes, these programmable bits affect the timer operation differently:
Table 42-6. Time modes and programmable bits
Mode Which programmable bits affect timer operations
32-bit Periodic Counter All bits (TSOT, TSOI, TROT) affect the timer operation as described previously.
Dual 16-bit Periodic
Counter
32-bit Trigger
Accumulator
• Only the TSOI bit controls the timer function.
• TROT and TSOT bits have no effect on timer operations.
32-bit Input Trigger
Capture • Only TSOI and TROT bits control the timer function.
• TSOT bit has no effect on timer operations.
42.5.5 Channel Chaining
Individual timer channels can be chained together to achieve a larger value of timeout.
Chaining the timer channel causes them to work in a 'nested loop' manner thereby leading
to an effective timeout value of TVAL
CHn
× (TVAL
CHn-1
+ 1).
Chapter 42 Low Power Interrupt Timer (LPIT)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1321