NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 644 / 1761

29.3.1.4.4 Fields
Field Function
31-2
PHYADDR
Physical Address
PHYADDR represents bits [31:2] of the system address.
CSAR[31:11] bits are used for tag compare
CSAR[10:4] bits are used to access the tag arrays
CSAR[10:2] bits are used to access the data arrays
1
—
Reserved
0
LGO
Initiate Cache Line Command
Setting this bit initiates the cache line command indicated by bits 27-24. Reading this bit indicates if a line
command is active
NOTE: This bit stays set until the command completes. Writing zero has no effect.
NOTE: This bit is shared with CLCR[LGO]
0b - Write: no effect. Read: no line command active.
1b - Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
29.3.1.5 Cache read/write value register (PCCCVR)
29.3.1.5.1 Offset
Register Offset
PCCCVR Ch
29.3.1.5.2 Function
The CCVR register is used to source write data or return read data for the commands
specified in the CLCR register.
Memory Map/Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
644 NXP Semiconductors