NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1575 / 1761

Offset Register Width
(In bits)
Access Reset value
14h Rx 14 Mask register (RX14MASK) 32 RW Table 49-5
18h Rx 15 Mask register (RX15MASK) 32 RW Table 49-5
1Ch Error Counter (ECR) 32 RW 0000_0000h
20h Error and Status 1 register (ESR1) 32 W1C 0000_0000h
28h Interrupt Masks 1 register (IMASK1) 32 RW 0000_0000h
30h Interrupt Flags 1 register (IFLAG1) 32 W1C 0000_0000h
34h Control 2 register (CTRL2) 32 RW 00A0_0000h
38h Error and Status 2 register (ESR2) 32 RO 0000_0000h
44h CRC register (CRCR) 32 RO 0000_0000h
48h Rx FIFO Global Mask register (RXFGMASK) 32 RW Table 49-7
4Ch Rx FIFO Information register (RXFIR) 32 RO Table 49-7
50h CAN Bit Timing register (CBT) 32 RW 0000_0000h
880h - 8FCh Rx Individual Mask registers (RXIMR0 - RXIMR31) 32 RW Table 49-7
B00h Pretended Networking Control 1 register (CTRL1_PN) 32 RW 0000_0100h
B04h Pretended Networking Control 2 register (CTRL2_PN) 32 RW 0000_0000h
B08h Pretended Networking Wake Up Match register (WU_MTC) 32 W1C 0000_0000h
B0Ch Pretended Networking ID Filter 1 register (FLT_ID1) 32 RW 0000_0000h
B10h Pretended Networking DLC Filter register (FLT_DLC) 32 RW 0000_0008h
B14h Pretended Networking Payload Low Filter 1 register (PL1_LO) 32 RW 0000_0000h
B18h Pretended Networking Payload High Filter 1 register (PL1_HI) 32 RW 0000_0000h
B1Ch Pretended Networking ID Filter 2 Register / ID Mask register (FLT_
ID2_IDMASK) 32 RW 0000_0000h
B20h Pretended Networking Payload Low Filter 2 Register / Payload Low
Mask register (PL2_PLMASK_LO) 32 RW 0000_0000h
B24h Pretended Networking Payload High Filter 2 low order bits / Payload
High Mask register (PL2_PLMASK_HI) 32 RW 0000_0000h
B40h Wake Up Message Buffer register for C/S (WMB0_CS) 32 RO 0000_0000h
B44h Wake Up Message Buffer Register for ID (WMB0_ID) 32 RO 0000_0000h
B48h Wake Up Message Buffer Register for Data 0-3 (WMB0_D03) 32 RO 0000_0000h
B4Ch Wake Up Message Buffer Register Data 4-7 (WMB0_D47) 32 RO 0000_0000h
B50h Wake Up Message Buffer register for C/S (WMB1_CS) 32 RO 0000_0000h
B54h Wake Up Message Buffer Register for ID (WMB1_ID) 32 RO 0000_0000h
B58h Wake Up Message Buffer Register for Data 0-3 (WMB1_D03) 32 RO 0000_0000h
B5Ch Wake Up Message Buffer Register Data 4-7 (WMB1_D47) 32 RO 0000_0000h
B60h Wake Up Message Buffer register for C/S (WMB2_CS) 32 RO 0000_0000h
B64h Wake Up Message Buffer Register for ID (WMB2_ID) 32 RO 0000_0000h
B68h Wake Up Message Buffer Register for Data 0-3 (WMB2_D03) 32 RO 0000_0000h
B6Ch Wake Up Message Buffer Register Data 4-7 (WMB2_D47) 32 RO 0000_0000h
B70h Wake Up Message Buffer register for C/S (WMB3_CS) 32 RO 0000_0000h
B74h Wake Up Message Buffer Register for ID (WMB3_ID) 32 RO 0000_0000h
Table continues on the next page...
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1575