NXP Semiconductors MWCT101 S Series, Reference Manual

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29.3.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
29.3.1.5.4 Fields
Field Function
31-0
DATA
Cache read/write Data
For tag search, read or write:
• CCVR[31:11] bits are used for tag array R/W value
• CCVR[10:4] bits are used for tag set address on reads; unused on writes
• CCVR[3:2] bits are reserved
• CCVR[1] tag modify bit
• CCVR[0] tag valid bit
For data search, read or write:
• CCVR[31:0] bits are used for data array R/W value
29.3.1.6 Cache regions mode register (PCCRMR)
29.3.1.6.1 Offset
Register Offset
PCCRMR 20h
29.3.1.6.2 Function
The CRMR register allows you to demote the cache mode of various subregions within
the device's memory map. Demoting the cache mode reduces the cache function applied
to a memory region from write-back to write-through to non-cacheable. After a region is
demoted, its cache mode can only be raised by a reset, which returns it to its default state.
Chapter 29 Local Memory Controller (LMEM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 645